1. Field
Exemplary embodiments of the present invention relate to a memory module including a volatile memory and a nonvolatile memory.
2. Description of the Related Art
A memory cell of a volatile memory (for example, a DRAM) may include a transistor which serves as a switch and a capacitor which stores charges (data). Whether data of a memory cell is high (a logic 1) or low (a logic 0) is determined according to whether there is a charge in the capacitor of the memory cell, that is whether the voltage of the terminal of the capacitor is high or low.
Data may be retained without loss as long as the charges accumulated in the capacitors are maintained. However, because the charges stored in the capacitors diminish due to leakage current in the PN junction of an MOS transistor, or the like, data may be lost. In order to prevent loss of data, the data in the memory cell may be read before the data is lost and the capacitor may be recharged in conformity with the read data. The data of the memory cell may be retained when such an operation is cyclically repeated. This recharging process is referred to as a refresh operation.
The memory chips mounted in most memory modules, which are used in data processing systems such as personal computers (PC), work stations, server computers or communication systems, are volatile memories. While volatile memories may operate at high speed, they are likely to lose stored data since refresh operations cannot be performed if power is not supplied. In order to remove such concerns, a memory module having an NVDIMM (non-volatile dual in-line memory module) scheme has been disclosed in the art. The NVDIMM is a memory module in which volatile memory, nonvolatile memory and an emergency power supply are mounted. This prevents data from being lost due to host power failure through an operation of backing up the data of the volatile memory in the nonvolatile memory using the emergency power when the power of the host is unstable.